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The SynaptiCAD Product Suite includes the following products: TestBencher Pro, VeriLogger Extreme, VeriLogger Pro, BugHunter Pro, DataSheet Pro, WaveFormer Pro, WaveFormer Lite, Timing Diagrammer Pro, GigaWave Viewer, Vhdl2Verilog, and Verilog2Vhdl. A license is required for all versions.
TestBencher Pro is a graphical test bench generator that dramatically reduces the time required to create and maintain test benches. TestBencher Pro automates the most tedious aspects of test bench development, allowing you to focus on the design and operation of the test bench. This is accomplished by representing each bus transaction graphically and then automatically generating the code for each transaction.
BugHunter uses the SynaptiCAD graphical environment and supports all major HDL simulators. It has the ability to launch the simulator, provide single step debugging, unit-level test bench generation, streaming of waveform data, project management, and a hierarchy tree.
DataSheet Pro is SynaptiCAD's top of the line timing digaram editor, providing the ultimate environment for documentation professionals working with multi-diagram projects. Datasheet Pro's project management features allow users to efficiently combine diagrams from multiple engineers into one project with uniform formatting. Using Object Linking and Embedding (OLE), users can embed timing diagrams into other publishing programs.
WaveFormer Pro is a revolutionary new rapid-prototyping EDA tool that helps you design faster and with fewer mistakes. WaveFormer Pro enables you to automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing and perform Boolean level simulation without the need for schematics or simulation models.
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx.